1. Field of the Invention
This invention relates to a phase locked loop (PLL) type signal generating apparatus and, more particularly, to a signal generating apparatus of a type wherein a signal at a desired frequency is generated by a voltage controlled oscillator (VCO), through a stable and fast switching operation.
2. Description of the Related Art
Nowadays, PLL type signal generators are employed in a wide variety of devices, such as network analyzers and radio receivers, for example. This type of signal generator is made up of a phase detector, a loop filter, a VCO, and a frequency divider. An output signal from the VCO--being the output signal of the signal generator --is frequency divided by the frequency divider, and is then supplied to the phase detector, where it is compared with a reference signal, and the comparison result supplied, via the loop filter, to the VCO. In the VCO, the frequency of the output signal is controlled so that the phase difference between the frequency divided signal and the reference signal becomes zero, and locked at a desired frequency.
Some of such signal generators are capable of changing a frequency dividing ratio of the frequency divider. This type of the signal generator includes a register for latching the frequency dividing ratio as externally supplied. The register latches the frequency dividing ratio, i.e., the frequency setting data, when supplied with a clock signal as a latch signal from exterior. The latched frequency setting data is applied to the frequency divider, from the register. The latched data is also supplied to the VCO. A preset voltage value of the VCO is changed according to the supplied frequency setting data. Thus, in the signal generator of this type, in order to vary the frequency of the output signal, the frequency dividing ratio of the frequency divider and the preset voltage value of the VCO are changed by changing the frequency setting data.
The frequency divider of the signal generating apparatus is made up of a counter, for example. A pulse output every time the counter overflows, is supplied as a frequency dividing signal to the phase detector. The overflow pulse is also fed back to the frequency divider. At the timing of outputting the pulse, the frequency divider reloads the latched frequency setting data from the register. In this way, the frequency dividing operation is repeated in accordance with the reloaded data. Accordingly, if the frequency setting data newly set is latched into the register, this new frequency setting data is loaded into the frequency divider at the timing of the overflow pulse. Subsequently, the frequency divider will operate on the basis of the new frequency setting data.
Before such frequency setting data is supplied to the VCO, the data is converted into an analog signal by a digital to analog (D/A) converter. The D/A converter produces a preset voltage of the VCO, which amounts to the frequency setting data latched in the register. In this way, the preset voltage of the VCO is changed by changing the frequency setting data, to vary the frequency of the output signal.
The conventional signal generator latches the frequency setting data into the register in response to the external clock signal. Therefore, the preset voltage of the VCO is changed simultaneously with the change of the data in the register. The frequency divider fetches the data of the register only when the overflow pulse is generated. Therefore, if the frequency of the output signal is changed by changing the preset voltage in the VCO, the frequency divider continues the counting operation according to the the previous frequency dividing data till the next overflow pulse occurs.
When the clock pulse is input to the register immediately after the overflow pulse occurs, the preset voltage immediately becomes a voltage amounting to the frequency newly set. However, the first time operation of the frequency divider is performed on the basis of the previous frequency dividing ratio, i.e., the dividing ratio before the frequency is switched. Therefore, the frequency divided signal output from the frequency divider will have a large phase difference with respect to the reference signal. This phase error varies depending on the timings of the clock pulse for the register and the overflow pulse of the frequency divider. In the PLL, the longer the pull-in operation, the larger the phase error. The times taken for the frequency changing are varied due to the timings of these two pulses, resulting in an unstable operation of the signal generator.